Phase locked loops are commonly used on various circuit applications, and may be used as clock multipliers or clock sources. For instance, an input clock of 10 MHz can be multiplied by a phase locked loop to yield a signal at 1 GHz, preferably in phase alignment with the 10 MHz clock signal.
In electronic systems, good clock distribution is very important to the overall performance of the product. Unwanted clock skew and jitter are two phenomena that may result from poor clock distribution, thus causing problems in the design and operation of the electronic systems. Techniques have been developed using phase locked loops (PLLs) to successfully manage these problems and reduce both to manageable levels, and PLLs are widely used in electronic circuits.
Conventional phase lock loops are discussed in many publications, examples of which include “PLL Synthesizers: A Switching Speed Tutorial”, Bar-Giora Goldberg, Microwave Journal, September 2001, see http://www.peregrine-semi.com/pdf_pll_switching_speed_giora.pdf. Further examples include Robert Adler, “A Study of Locking Phenomena in Oscillators” Proceedings of the IEEE, October 1973, pp. 1380-1385; Roland Best, “Phase Lock Loops”, McGraw-Hill, New York, 1984; and “Electronic Circuits Design and Applications”, U. Tietze, Ch. Schenk, Springer-Verlag (1991) pp. 164-167.
A typical phase locked loop circuit is shown in FIG. 1, having a phase/frequency detector, a charge pump, a filter, a voltage controlled oscillator (VCO) or variable frequency oscillator (VFO), and a divider (shown to divide by N). The phase/frequency detector sends to the filter information about the frequency and phase of the reference signal relative to the feedback clock signal. The filter integrates this information into a voltage. The VCO converts the voltage information into a higher speed/frequency output signal, which is fed back into the phase/frequency detector through the divider. The divider takes the higher speed frequency and divides it down for comparison to the reference signal by the phase/frequency detector.
As recognized by the present inventors, it is desirable to reduce the lock time for PLLs in certain applications, such as frequency synthesizers. For example, when frequency hopping is used in modern wireless networks (for example, 3G cellular, WCDMA, WLAN, and Bluetooth), the time to settle is considered “dead time” where no information is transmitted, and thus time is wasted. Speeding up the lock time increases the effective data rate and thus the value of such networks. Another example would be in wireline networks, where a reduced lock time helps to minimize the amount of data lost. That is, if a long string of zeros or ones is in the data path and the PLL loses lock, reacquiring lock sooner results in more data recovered.
A conventional way to speed up a PLL 20 is shown in FIG. 2 and includes a second charge-pump (CP) 32, or extra current sources, in parallel with a first charge pump 28 but with more current. This additional source 32 of current helps charge or discharge the main capacitor, or loop filter capacitor, faster and thus increases the loop bandwidth. However, since this changes the loop dynamics, the PLL 20 may more easily become unstable and oscillate. Conventional attempts to restore stability, such as switching in resistors to reduce the loop bandwidth, change the loop dynamics themselves and further add to the settling time of the PLL. Stability is therefore a major disadvantage of using conventional PLL speed-up techniques.
Additionally, conventional techniques to speed up PLL lock time may require some method of determining when the PLL is locked so that the added charge pump or current source can be disconnected for final lock, such as lock-detector circuitry. This adds cost and complexity to the design, and is an additional disadvantage of conventional techniques to speed up PLL lock times.
Furthermore, conventional techniques to speed up PLL lock times do not prevent frequency runaway of the locked PLL. Frequency runaway occurs when a locked PLL comes out of lock and cannot re-acquire lock.
As recognized by the present inventors, what is needed is a circuit and method for reducing the lock-time of a phase lock loop circuit without changing the feedback loop characteristics.
It is against this background that various embodiments of the present invention were developed.